`timescale 1ps/1ps
module sbox4(
    input  [2:0]   cmd  // {ende  sel}
,   input  [127:0] in
,   output [31:0]  out    
);

reg  [31:0] cur_sbox_in;// 选择
wire [31:0] cur_sbox_out;// 

always @(*) begin
    case(cmd[1:0])
        2'b00:cur_sbox_in = in[127:96];
        2'b01:cur_sbox_in = in[ 95:64];
        2'b10:cur_sbox_in = in[ 63:32];
        2'b11:cur_sbox_in = in[ 31: 0];
    endcase
end

sbox sbox_u0({cmd[2],cur_sbox_in[31:24]},cur_sbox_out[31:24]);
sbox sbox_u1({cmd[2],cur_sbox_in[23:16]},cur_sbox_out[23:16]);
sbox sbox_u2({cmd[2],cur_sbox_in[15: 8]},cur_sbox_out[15: 8]);
sbox sbox_u3({cmd[2],cur_sbox_in[ 7: 0]},cur_sbox_out[ 7: 0]);

assign out = cur_sbox_out;

endmodule